1. Field of the Invention
This application is related to data processing systems and more particularly to video data processing systems.
2. Description of the Related Art
A typical video data processing system includes an off-chip, system memory and a video system-on-a-chip (SOC) integrated circuit including multiple video processing blocks and related hardware. The video SOC receives compressed video data and decompresses (i.e., decodes, uncompresses, or expands) the compressed video data to recover uncompressed (i.e., raw) video data. The video SOC writes the uncompressed video data to the system memory for subsequent use by one or more video processing blocks. The one or more video processing blocks retrieve the uncompressed video data and may write processed, uncompressed video data back to memory. In general, a video image includes R×C pixels (e.g., 1920×1080 for an exemplary high-definition video screen) and each pixel may be represented by multiple bytes of data. Due to the large quantity of data involved, a full frame of video data of a video image is not typically available to a particular video processing block at a particular time. Rather, portions of the frame of video data are read from system memory, processed incrementally, and, in some cases, written back to memory.
Movement of uncompressed video data between the system memory and the video SOC consumes substantial memory bandwidth. Typically, the memory bandwidth available to the video SOC limits performance of the video processing system. Increases to the system memory (e.g., by increasing the number of memory channels), which may increase the available memory bandwidth, introduce substantial additional costs to the video SOC (e.g., by increasing the size of on-chip buffers, controllers, number of pins, and board area), increases the cost of external memory, and ultimately increases the cost of the video processing system.